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ISL85033
condition has cleared. If the overcurrent fault counter overflows
during soft-start, the converter shuts down and this hiccup mode
operation repeats.
Thermal Overload Protection
Thermal overload protection limits maximum junction
temperature in the ISL85033. When the junction temperature
(T J ) exceeds +150°C, a thermal sensor sends a signal to the fault
monitor.
The fault monitor commands the buck regulator to shut down.
When the junction temperature has decreased by 20°C, the
regulator will attempt a normal soft-start sequence and return to
Synchronization Control
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNCIN pin. The falling edge on
the SYNCIN triggers the rising edge of PHASE1/2. The switching
frequency for each output is half of the SYNCIN frequency.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, Δ I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 5:
V IN – V OUT V OUT
Fs × Δ I
normal operation. For continuous operation, the +125°C
junction temperature rating should not be exceeded.
L = ---------------------------- × -------------
V IN
(EQ. 5)
BOOT Undervoltage Protection
If the BOOT capacitor voltage falls below 2.5V, the BOOT
undervoltage protection circuit will pull the phase pin low through
a 1 ? switch for 400ns to recharge the capacitor. This operation
may arise during long periods of no switching as in no load
situations.
Application Guidelines
Operating Frequency
The ISL85033 operates at a default switching frequency of
500kHz if FS is tied to VCC. Tie a resistor from FS to GND to
program the switching frequency from 300kHz to 2MHz, as
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it will not saturate in
overcurrent conditions.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
shown in Equation 4.
R FS [ k Ω ] = 122k Ω? ( t – 0.17 μ s )
Where:
t is the switching period in μs.
300
200
100
(EQ. 4)
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
V OUTripple = -----------------------------------
0
500 750 1000 1250 1500
FS (kHz)
FIGURE 43. R FS SELECTION vs FS
1750
2000
For the ceramic capacitors (low ESR): =
Δ I
8 ? F SW ? C OUT
(EQ. 6)
where Δ I is the inductor’s peak to peak ripple current, F SW is the
switching frequency and C OUT is the output capacitor.
If using electrolytic capacitors then:
18
V OUTripple = Δ I*ESR
(EQ. 7)
FN6676.6
February 23, 2012
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